Semiconductor device and method of formation

ABSTRACT

A semiconductor device and method of formation are provided. The semiconductor device includes a channel surrounding a dielectric tube and a gate surrounding the channel. The dielectric tube comprises a high dielectric constant material that has or conducts few to no carriers, such as electrons or holes. The presence of the dielectric tube confines carriers to the channel, which is in close proximity to the gate. The proximity of the channel, and the carriers therein, to the gate affords greater control to the gate over the carriers, thus allowing a length of the channel to be decreased while experiencing little to no short channel effects, such as current leakage through the channel.

RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No. 15/906,226 titled “SEMICONDUCTOR DEVICE AND METHOD OF FORMATION” and filed on Feb. 27, 2018, now U.S. Pat. No. 10,461,165, which is a divisional of and claims priority to U.S. patent application Ser. No. 14/321,983, titled “SEMICONDUCTOR DEVICE AND METHOD OF FORMATION” and filed on Jul. 2, 2014, now U.S. Pat. No. 9,917,169 issued Mar. 13, 2018, each is incorporated herein by reference

BACKGROUND

In a semiconductor device, such as a transistor, current flows through a channel region between a source region and a drain region upon application of a sufficient voltage or bias to a gate of the device. When current flows through the channel region, the transistor is generally regarded as being in an ‘on’ state, and when current is not flowing through the channel region, the transistor is generally regarded as being in an ‘off’ state.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is an illustration of a perspective view of a semiconductor device at a stage of fabrication, in accordance with some embodiments.

FIG. 2 is an illustration of a cross sectional view of a semiconductor device at a stage of fabrication, in accordance with some embodiments.

FIG. 3 is an illustration of a perspective view of a semiconductor device at a stage of fabrication, in accordance with some embodiments.

FIG. 4 is an illustration of a top down view of a semiconductor device at a stage of fabrication, in accordance with some embodiments.

FIG. 5 is an illustration of a cross sectional view of a semiconductor device at a stage of fabrication, in accordance with some embodiments.

FIG. 6 is an illustration of a perspective view of a semiconductor device at a stage of fabrication, in accordance with some embodiments.

FIG. 7 is an illustration of a top down view of a semiconductor device at a stage of fabrication, in accordance with some embodiments.

FIG. 8 is an illustration of a cross sectional view of a semiconductor device at a stage of fabrication, in accordance with some embodiments.

FIG. 9 is an illustration of a perspective view of a semiconductor device at a stage of fabrication, in accordance with some embodiments.

FIG. 10 is an illustration of a top down view of a semiconductor device at a stage of fabrication, in accordance with some embodiments.

FIG. 11 is an illustration of a cross sectional view of a semiconductor device at a stage of fabrication, in accordance with some embodiments.

FIG. 12 is an illustration of a perspective view of a semiconductor device at a stage of fabrication, in accordance with some embodiments.

FIG. 13 is an illustration of a top down view of a semiconductor device at a stage of fabrication, in accordance with some embodiments.

FIG. 14 is an illustration of a cross sectional view of a semiconductor device at a stage of fabrication, in accordance with some embodiments.

FIG. 15 is an illustration of a top down view of a semiconductor device at a stage of fabrication, in accordance with some embodiments.

FIG. 16 is an illustration of a cross sectional view of a semiconductor device at a stage of fabrication, in accordance with some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

One or more techniques for forming a semiconductor device and resulting structures formed thereby are provided herein. Some embodiments of the present disclosure have one or a combination of the following features and/or advantages.

According to some embodiments, a semiconductor device comprises a channel surrounding a dielectric tube. In some embodiments, the channel comprises silicon. In some embodiments, the dielectric tube comprises at least one of silicon or oxide and less than 1% germanium. In some embodiments, a gate surrounds the channel. In some embodiments, a ratio of a channel thickness of the channel divided by a channel length of the channel is between about 1/30 to about 10. In some embodiments, the channel thickness is between about 1 nm to about 30 nm. In some embodiments, the channel length is between about 3 nm to about 30 nm. In some embodiments, the dielectric tube has a tube width between about 3 nm to about 100 nm. In some embodiments, the channel thickness is independent of the tube width, such that a channel region comprising the channel can comprise any tube width without altering the channel thickness.

According to some embodiments, a method of forming the semiconductor device comprises forming a first tube material layer over a first channel material layer. In some embodiments, the first channel material layer is over a dielectric layer. In some embodiments, the first channel material layer is formed by forming a layer of silicon over the dielectric layer. In some embodiments, the first tube material layer is formed by growing a layer of at least one of silicon or germanium over the first channel material layer. In some embodiments, a first column is formed from the first tube material layer to form a first tube material and from the first channel material layer to form a first channel material. In some embodiments, the first tube material is over the first channel material. In some embodiments, a second channel material is formed over the first tube material such that the second channel material is in contact with the first channel material. In some embodiments, the second channel material is formed by performing at least one of chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), etc. In some embodiments, the second channel material comprises silicon. In some embodiments, at least some of the dielectric layer is removed from under the first channel material to form a first gate opening. In some embodiments, the gate is formed in the first gate opening under the first channel material and around the second channel material. In some embodiments, an annealing operation is performed to form the dielectric tube from the first tube material and to form the channel from the first channel material and the second channel material.

According to some embodiments, the annealing operation comprises oxidizing the first tube material to form the dielectric tube. In some embodiments, few to no carriers, such as electrons or holes, are in or traverse the dielectric tube, such that the presence of the dielectric tube substantially limits or confines electrons or electron holes to the channel, where the channel is in close proximity to the gate, as compared to a semiconductor device that does not comprise a dielectric tube and thus does not limit carriers to an area in close proximity to the gate. In some embodiments, promoting location of carriers to an area in close proximity to the gate allows the gate to have greater control over carriers, which in turn allows the channel to be made shorter while inhibiting short channel effects, such as current leakage between a first active area comprising at least one of a source or a drain and a second active area comprising at least one of a source or a drain, as compared to a semiconductor device where carriers are not confined to an area in close proximity to the gate.

FIGS. 1, 3, 6, 9 and 12 are perspective views of a semiconductor device 100, FIGS. 4, 7, 10, 13 and 15 are top down views of the semiconductor device 100, and FIGS. 2, 5, 8, 11, 14 and 16 are cross-sectional views of the semiconductor device 100, according to some embodiments, at various stages of fabrication. Turning to FIGS. 1 and 2, where FIG. 2 illustrates a cross section of the semiconductor device 100 taken along line 2-2 in FIG. 1, according to some embodiments. In some embodiments, a first channel material layer 104 a is formed over a dielectric layer 102, according to some embodiments. In some embodiments, the dielectric layer 102 comprises at least one of an oxide, a nitride, etc. In some embodiments, the dielectric layer 102 includes at least one of an epitaxial layer, a silicon-on-insulator (SOI) structure, a wafer, or a die formed from a wafer. In some embodiments, the dielectric layer 102 is over a substrate (not shown). In some embodiments, the substrate comprises at least one of silicon, germanium, carbon, etc. In some embodiments, the substrate includes at least one of an epitaxial layer, a silicon-on-insulator (SOI) structure, a wafer, or a die formed from a wafer. In some embodiments, the first channel material layer 104 a comprises at least one of silicon, germanium, carbon, etc. In some embodiments, a first tube material layer 106 a is formed over the first channel material layer 104 a. In some embodiments, the first tube material layer 106 a is grown, such as by epitaxial growth. In some embodiments, the first tube material layer 106 a comprises at least one of silicon, germanium, etc. In some embodiments, the first channel material layer 104 a and the first tube material layer 106 a comprise different materials. In some embodiments, the first channel material layer 104 a has a first channel material height 103 a between about 1 nm to about 30 nm. In some embodiments, the first tube material layer 106 a has a first tube material height 105 a between about 3 nm to about 100 nm.

Turning to FIGS. 3, 4 and 5, where FIG. 5 illustrates a cross section of the semiconductor device 100 taken along line 5-5 in FIGS. 3 and 4, according to some embodiments. In some embodiments, the first channel material layer 104 a is patterned to form a first channel material 104 and the first tube material layer 106 a is patterned to form a first tube material 106. In some embodiments, the first channel material 104 and the first tube material 106 comprises a first column 101. In some embodiments, the first column 101 has a first column width 105 b. In some embodiments, the first column width 105 b is between about 3 nm to about 100 nm. In some embodiments, the first tube material 106 has the first tube material height 105 a. In some embodiments, a width of the first tube material 106 is substantially equal to a width of the first channel material 104. In some embodiments, such as illustrated in FIG. 5, the first channel material 104 has the first channel material height 103 a.

Turning to FIGS. 6, 7 and 8, where FIG. 8 illustrates a cross section of the semiconductor device 100 taken along line 8-8 in FIGS. 6 and 7, according to some embodiments. In some embodiments, a second channel material 108 is formed over the first column 101, such that a portion of the second channel material 108 is in contact with a portion of the first channel material 104. In some embodiments, the second channel material 108 is grown. In some embodiments, the second channel material 108 comprises at least one of silicon, germanium, carbon, etc. In some embodiments, the second channel material 108 comprises a same or similar material as the first channel material 104. In some embodiments, such as illustrated in FIG. 8, the second channel material 108 has a channel material thickness 108 c between about 1 nm to about 30 nm.

According to some embodiments, such as illustrated in FIGS. 6 and 7, the first channel material 104, the first tube material 106, and the second channel material 108 comprise a semiconductor column 107. In some embodiments, the semiconductor column 107 comprises a first active area 107 b coupled to a first end of a channel region 107 a, the channel region 107 a, and a second active area 107 c coupled to a second end of the channel region 107 a. In some embodiments, the first active area 107 b comprises at least one of a source or a drain. In some embodiments, the first active area 107 b comprises at least one of a first conductivity type or a second conductivity type. In some embodiments, the second active area 107 c comprises at least one of a source or a drain. In some embodiments, the second active area 107 c comprises at least one of a first conductivity type or a second conductivity type. In some embodiments, the first conductivity type comprises at least one of n-type or p-type. In some embodiments, the first conductivity type comprises n-type when the second conductivity type comprises p-type and the second conductivity type comprises n-type when the first conductivity type comprises p-type. In some embodiments, the semiconductor column 107 has a column height 108 a between about 4 nm to about 130 nm. In some embodiments, the semiconductor column 107 has a column width 108 b between about 4 nm to about 130 nm. In some embodiments, such as illustrated in FIGS. 6 and 7, a photoresist 110 is formed over at least one of the first active area 107 b or the second active area 107 c, such that the channel region 107 a is exposed. In some embodiments, the first tube material 106 is removed from over the first channel material 104 in at least one of the first active area 107 b or the second active area 107 c prior to forming the second channel material 108. In some embodiments, the second channel material 108 is thus over or around merely the first channel material 104 in at least one of the first active area 107 b or the second active area 107 c, but is over or around both the first tube material 106 and the first channel material 104 in the channel region 107 a.

Turning to FIGS. 9, 10 and 11, where FIG. 11 illustrates a cross section of the semiconductor device 100 taken along line 11-11 in FIGS. 9 and 10, according to some embodiments. In some embodiments, at least some of the dielectric layer 102 is removed from under the first channel material 104 to form a first gate opening 112. In some embodiments, at least some of the dielectric layer 102 is removed by a selective etch, where the selective etch is selective for the dielectric layer 102. In some embodiments, the selective etch comprises a first etchant. In some embodiments, the first etchant is at least one of hydrogen, fluorine, nitrogen, etc. In some embodiments, the selective etch removes little to none of the first channel material 104 and little to none the second channel material 108. In some embodiments, the first gate opening 112 extends under at least some of the channel region 107 a of the semiconductor column 107.

Turning to FIGS. 12, 13 and 14, where FIG. 14 illustrates a cross section of the semiconductor device 100 taken along line 14-14 in FIGS. 12 and 13, according to some embodiments. In some embodiments, a gate 114 is formed around at least some of the channel region 107 a of the semiconductor column 107. In some embodiments, the gate 114 surrounds and is in contact with the first channel material 104 and the second channel material 108. In some embodiments, the gate 114 comprises a gate dielectric (not shown) surrounded by a gate electrode. In some embodiments, the gate dielectric is in contact with at least one of the first channel material 104 or the second channel material 108 in the channel region 107 a. In some embodiments, the gate dielectric comprises a high dielectric constant material, such as oxide. In some embodiments, the gate electrode comprises a conductive material, such as metal. In some embodiments, the gate 114 is formed by deposition, such as at least one of CVD, ALD, PVD, etc.

Turning to FIGS. 15 and 16, where FIG. 16 illustrates a cross section of the semiconductor device 100 taken along line 16-16 in FIG. 15, according to some embodiments. In some embodiments, an annealing operation is performed to form a dielectric tube 116 from the first tube material 106. In some embodiments, the photoresist 110 is removed prior to the annealing operation. In some embodiments, the photoresist 110 is removed after the annealing operation. In some embodiments, the annealing operation forms a channel 118 from at least one of the first channel material 104 or the second channel material 108. In some embodiment, the channel 118 has a channel thickness 118 c between about 1 nm to about 30 nm. In some embodiment, the channel 118 has a channel height 118 a between about 4 nm to about 130 nm. In some embodiment, the channel 118 has a channel width 118 b between about 4 nm to about 130 nm. In some embodiment, the channel 118 has a channel length 118 d. In some embodiments, the channel length 118 d comprises a distance between the first active area 107 b and the second active area 107 c. In some embodiments, the channel length 118 d is between about 3 nm to about 30 nm. In some embodiments, a ratio of the channel thickness 118 c of the channel 118 divided by the channel length 118 d of the channel 118 is between about 1/30 to about 10. In some embodiment, the dielectric tube 116 has a tube height 116 a between about 3 nm to about 100 nm. In some embodiment, the dielectric tube 116 has a tube width 116 b between about 3 nm to about 100 nm. In some embodiments, the dielectric tube 116 has a shape when viewed in FIG. 16. In some embodiments, the shape is at least one of square, oval, polygonal, triangular, etc.

According to some embodiments, the annealing operation oxidizes the first tube material 106, such that the dielectric tube 116 comprises at least one of silicon, oxide, etc., and less than 1% germanium. In some embodiments, the annealing operation comprises applying an oxide precursor at a flow rate between about 1 sccm to about 100 sccm. In some embodiments, the annealing operation occurs at a first temperature between about 600° C. to about 1,000° C. for a first annealing duration between about is to about 1 min. In some embodiments, the annealing operation occurs at a first pressure between about 1 torr to about 1,000 torr.

According to some embodiments, the presence of the dielectric tube 116 constrains the location of carriers, such as electrons or holes, to an area in closer proximity to the gate 114, as compared to a semiconductor device that does not have a channel surrounding a dielectric tube. In some embodiments, given the proximity of the gate 114 to the carriers, the gate is able to exert greater control over the carriers. In the some embodiments, the greater control afforded the gate allows the channel to have a shorter channel length while mitigating short channel effects, such as current leakage between the first active area 107 b and the second active area 107 c.

According to some embodiments, a semiconductor device comprises a channel surrounding a dielectric tube and a gate surrounding the channel. In some embodiments, a ratio of a channel thickness of the channel divided by a channel length of the channel is between about 1/30 to about 10.

According to some embodiments, a method of forming a semiconductor device comprises forming a first tube material over a first channel material. In some embodiments, the first channel material is over a dielectric layer. According to some embodiments, the method of forming a semiconductor device comprises forming a second channel material over the first tube material such that the second channel material is in contact with the first channel material and removing at least some of the dielectric layer from under the first channel material to form a first gate opening. According to some embodiments, the method of forming a semiconductor device comprises forming a gate in the first gate opening under the first channel material and around the second channel material and performing an annealing operation to form a dielectric tube from the first tube material and to form a channel from the first channel material and the second channel material.

According to some embodiments, a semiconductor device comprises a channel surrounding a dielectric tube. In some embodiments, the dielectric tube comprises at least one of silicon or oxide and less than 1% germanium. In some embodiments, a gate surrounds the channel.

The foregoing outlines features of several embodiments so that those of ordinary skill in the art may better understand various aspects of the present disclosure. Those of ordinary skill in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of various embodiments introduced herein. Those of ordinary skill in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Although the subject matter has been described in language specific to structural features or methodological acts, it is to be understood that the subject matter of the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing at least some of the claims.

Various operations of embodiments are provided herein. The order in which some or all of the operations are described should not be construed to imply that these operations are necessarily order dependent. Alternative ordering will be appreciated having the benefit of this description. Further, it will be understood that not all operations are necessarily present in each embodiment provided herein. Also, it will be understood that not all operations are necessary in some embodiments.

It will be appreciated that layers, features, elements, etc. depicted herein are illustrated with particular dimensions relative to one another, such as structural dimensions or orientations, for example, for purposes of simplicity and ease of understanding and that actual dimensions of the same differ substantially from that illustrated herein, in some embodiments. Additionally, a variety of techniques exist for forming the layers, regions, features, elements, etc. mentioned herein, such as at least one of etching techniques, planarization techniques, implanting techniques, doping techniques, spin-on techniques, sputtering techniques, growth techniques, or deposition techniques such as chemical vapor deposition (CVD), for example.

Moreover, “exemplary” is used herein to mean serving as an example, instance, illustration, etc., and not necessarily as advantageous. As used in this application, “or” is intended to mean an inclusive “or” rather than an exclusive “or”. In addition, “a” and “an” as used in this application and the appended claims are generally be construed to mean “one or more” unless specified otherwise or clear from context to be directed to a singular form. Also, at least one of A and B and/or the like generally means A or B or both A and B. Furthermore, to the extent that “includes”, “having”, “has”, “with”, or variants thereof are used, such terms are intended to be inclusive in a manner similar to the term “comprising”. Also, unless specified otherwise, “first,” “second,” or the like are not intended to imply a temporal aspect, a spatial aspect, an ordering, etc. Rather, such terms are merely used as identifiers, names, etc. for features, elements, items, etc. For example, a first element and a second element generally correspond to element A and element B or two different or two identical elements or the same element.

Also, although the disclosure has been shown and described with respect to one or more implementations, equivalent alterations and modifications will occur to others of ordinary skill in the art based upon a reading and understanding of this specification and the annexed drawings. The disclosure comprises all such modifications and alterations and is limited only by the scope of the following claims. In particular regard to the various functions performed by the above described components (e.g., elements, resources, etc.), the terms used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure. In addition, while a particular feature of the disclosure may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application. 

What is claimed is:
 1. A semiconductor device comprising: a dielectric layer; a first semiconductor layer over the dielectric layer; a second semiconductor layer over the first semiconductor layer, wherein the first semiconductor layer directly contacts the second semiconductor layer, the first semiconductor layer and the second semiconductor layer having a first source/drain region, a second source/drain region and a channel region interposed between the first source/drain region and the second source/drain region; a dielectric tube interposed between the first semiconductor layer and the second semiconductor layer in the channel region along a line perpendicular to a shortest line between the first source/drain region and the second source/drain region; and a gate structure over the second semiconductor layer and below the first semiconductor layer in the channel region.
 2. The semiconductor device of claim 1, wherein the first source/drain region is free of the dielectric tube.
 3. The semiconductor device of claim 2, wherein the second source/drain region is free of the dielectric tube.
 4. The semiconductor device of claim 3, wherein a length of the dielectric tube from the first source/drain region to the second source/drain region is between about 3 nm to about 30 nm.
 5. The semiconductor device of claim 1, wherein the second semiconductor layer extends along sidewalls of the first semiconductor layer.
 6. The semiconductor device of claim 1, wherein the gate structure extends below an upper surface of the dielectric layer.
 7. A semiconductor device comprising: a first source/drain region; a second source/drain region; a dielectric tube interposed between the first source/drain region and the second source/drain region in a first direction; a semiconductor material, wherein the dielectric tube is completely surrounded by the semiconductor material in a second direction, wherein the second direction is perpendicular to the first direction, the semiconductor material comprising a channel region electrically interposed between the first source/drain region and the second source/drain region; and a gate structure over the semiconductor material.
 8. The semiconductor device of claim 7, wherein the gate structure completely surrounds the semiconductor material in the second direction.
 9. The semiconductor device of claim 7 further comprising a dielectric layer, wherein the gate structure extends into an indent in an upper surface of the dielectric layer.
 10. The semiconductor device of claim 9, wherein a bottommost surface of the semiconductor material is above an uppermost surface of the dielectric layer.
 11. The semiconductor device of claim 9, wherein the dielectric layer extends completely under the first source/drain region and the second source/drain region.
 12. The semiconductor device of claim 7, wherein the semiconductor material comprises silicon and the dielectric tube comprises silicon oxide.
 13. The semiconductor device of claim 12, wherein the semiconductor material comprises less than 1% germanium.
 14. The semiconductor device of claim 13, wherein the semiconductor material comprises: a first semiconductor layer below the dielectric tube; and a second semiconductor layer over sidewalls and a top surface of the dielectric tube.
 15. The semiconductor device of claim 14, wherein the second semiconductor layer extends along sidewalls of the first semiconductor layer.
 16. A semiconductor device comprising: a first semiconductor layer; a second semiconductor layer over the first semiconductor layer, wherein the first semiconductor layer directly contacts the second semiconductor layer, the first semiconductor layer and the second semiconductor layer having a first source/drain region, a second source/drain region and a channel region interposed between the first source/drain region and the second source/drain region; a first dielectric layer interposed between the first semiconductor layer and the second semiconductor layer in the channel region in a direction perpendicular to current flow between the first source/drain region and the second source/drain region; and a gate structure over the second semiconductor layer.
 17. The semiconductor device of claim 16, wherein the first dielectric layer extends into the first source/drain region and the second source/drain region.
 18. The semiconductor device of claim 16 further comprising a second dielectric layer, wherein the first semiconductor layer and the second semiconductor layer are over the second dielectric layer.
 19. The semiconductor device of claim 18, wherein the gate structure contacts the second dielectric layer.
 20. The semiconductor device of claim 18, wherein the first dielectric layer comprises silicon oxide comprising germanium, the germanium being less than 1% of the first dielectric layer. 